1. Field of the Invention
The present invention relates to a sense amplifier being used in a semiconductor memory. More particularly, the present invention relates to a sense amplifier controlling circuit and a controlling method suitable for reading and rewriting control of a sense amplifier on which a preamplifier is mounted.
Priority is claimed on Japanese Patent Application No. 2007-280509, filed Oct. 29, 2007, the content of which is incorporated herein by reference in its entirety.
2. Description of Related Art
With the development of recent digital technology, a digitalized portable device such as a cellular phone or a portable media player has been manufactured and rapid technical innovation in this connection has been achieved. Such technical innovation for the portable device has achieved device miniaturization and long operating time, in addition to the improvement of processing performance. The portable device miniaturization and long operating time need miniaturization and high performance of batteries mounted on the portable device. However, these are contradictory factors, and thus it is difficult to achieve both at a high level. For this reason, a semiconductor memory mounted on a portable device particularly needs low voltage and low power consumption with a large effect.
Dynamic random access memory (DRAM), which is a kind of a semiconductor memory, requires a periodical memory holding operation. Memory cells, which are memory elements, flow a very small amount of leakage current. For this reason, the amount of information of memory cells decreases with the passage of time. When the decreased amount exceeds a limit value, data is not correctly read. In other words, data is destroyed. In order to prevent this, there is performed a memory holding operation that drives a sense amplifier at constant time intervals and returns data amplified again to memory cells. This memory holding operation has large power consumption in operations of DRAM. In connection with DRAM used in a portable device, the important problem is how to reduce this power consumption.
It is extremely important in terms of power consumption reduction to lower the operating voltage of the sense amplifier. However, the sense amplifier originally amplifies a differential electric potential of a pair of minute bit lines. Therefore, an operating speed has a large delay when lowering the operating voltage. Moreover, normal amplification is not possible. In order to guarantee the operation property of the sense amplifier at a low voltage, there is a method for reducing the threshold voltage (referred to as Vth) of a transistor (referred to as Tr) included in the sense amplifier. However, in the state where a differential electric potential amplification of a pair of bit lines is saturated, the sense amplifier leakage current flows from a flip-flop of a complementary metal-oxide semiconductor (CMOS), which is a main component thereof. The amount of leakage current becomes larger with decreasing Vth. Since the dependency of the amount of leakage current on Vth is not linear, the difference of Vth of dozens of % may give rise to the difference of leakage current amount of several digits. The increase of leakage currents leads to an increase of power consumption. Since a method for reducing Vth immediately has a limit, a countermeasure by a circuit system has been tried.
Japanese Unexamined Patent Application, First Publication, No. 2001-332087 (pages 6 to 9, FIG. 1) discloses a sense amplifier in which a kind of amplifier circuit is added to the CMOS flip-flop. The added amplifier circuit performs an amplification operation different from the CMOS flip-flop in an early stage of a sense operation. In other words, the sense amplifier provides a circuit technique performing a pre-sense. This additional amplifier circuit is below referred to as a preamplifier.
A preamplifier is an additional circuit. Therefore, there is a problem that the circuit area of the sense amplifier increases. The sense amplifier is a circuit with a large recurrence number. A slight increase of the sense amplifier area has an impact on the whole area of the semiconductor memory. Thus, it is desirable to configure a circuit in which the number of newly necessary components or control signals is small. The disclosed preamplifier requires seven transistors and two control signals in a dedicated manner.
A preamplifier is not a circuit that is very generally used, like a CMOS flip-flop. The preamplifier does not have a circuit configuration that is established as a standard. It is considered that various trials will be performed on the preamplifier in the future in this field. Therefore, the above reference is silent about a preamplifier that requires four transistors and one control signal in a dedicated manner. This is a circuit configuration in which mounting is comparatively easy in view of operation timing of the control signal.
As described above, with low voltage and low power consumption of the semiconductor memory, the sense amplifier has a problem that should be solved. The sense amplifier includes the CMOS flip-flop. As the operating voltage decreases, the voltage (Vgs) between a gate and a source approaches Vth. In this case, there is a phenomenon that the differential electric potential of a pair of bit lines cannot be amplified or the speed of amplification is largely late. In order to avoid this phenomenon, it is necessary to lower Vth by adjustment in a manufacturing process of the transistor. On the other hand, in a state where the sense operation terminates and the differential electric potential of the pair of bit lines is amplified to about the power supply voltage of the sense amplifier, the leakage current is generated from the sense amplifier. The leakage current flows from an N-channel transistor (referred to as Nch Tr) of the flip-flop to ground (GND). Moreover, the leakage current flows from the power supply of the sense amplifier to a P-channel transistor (referred to as Pch Tr) of the flip-flop. The leakage current becomes larger with decreasing Vth of Tr. Since it is difficult to simultaneously achieve lowering the operation voltage and the power consumption only by adjustment of Vth, a novel approach of circuit is necessary.
Hereinafter, a problem on a circuit design revealed by the present applicant will be described. As described above, there has been recently proposed a sense amplifier on which the above-described preamplifier is mounted. The preamplifier mainly operates in an early stage of the sense operation. Then, the preamplifier stops when the differential electric potential of the pair of bit lines is amplified. Whether or not the differential electric potential of the pair of bit lines is amplified and the speed by which the differential electric potential is amplified, are determined at an early stage of the sense operation. For this reason, a preamplifier in which Vth is lowered and thus the speed of amplification is improved is used in an early stage of the sense operation. When the differential electric potential of the pair of bit lines is amplified, the leakage current is restrained by only operation of the conventional sense amplifier.
The applicant makes clear some problems in the sense method using the preamplifier. Since the number of transistors included therein increases compared to that in the conventional sense amplifier without the preamplifier, one of the problems is that the circuit area increases. Since the sense amplifier has a high recurrence number, a slight increase of area has a large impact on the chip area of a semiconductor. In order to restrain the increase of a sense amplifier circuit area with respect to the increase of transistors, it is necessary to reduce the gate width of the transistor. In particular, a main role of the CMOS flip-flop is to hold the differential electric potential of the amplified pair of bit lines. It is preferable to reduce the gate width of the transistor from the viewpoint of the suppression of the leakage current.
However, the following drawback may occur when reducing the gate width of the transistor. In other words, a first problem when reducing the Tr gate width is that a read operation (a reading operation) is delayed. In a conventional sense amplifier without the preamplifier in the read operation, the Tr gate width cannot be reduced so much in order to guarantee a sense operating speed. Therefore, the conventional sense amplifier has the capability for driving an input-output (IO) line with a load larger than that of a bit line. On the other hand, since a sense amplifier mounting the preamplifier has a tendency to reduce the Tr gate width of the CMOS flip-flop as described above, there is a problem that the capability for driving the IO line is deteriorated compared to the conventional sense amplifier.
Here, the degradation of drive capability of the IO line when reducing the Tr gate width will be described with reference to FIG. 9. FIG. 9 is a signal waveform chart showing signal changes of a column switch line (column selection line) YS, complementary bit lines BL and /BL, and complementary IO lines IO and /IO. In this case, a memory cell made of Tr and a capacitor, and a sense amplifier made of a CMOS flip-flop are connected to the bit lines BL and /BL. Herewith, the IO lines IO and /IO are connected to the bit lines BL and /BL via two transistors that are turned on when the column switch line YS is a high level. In connection with a signal waveform of the IO line /IO shown in FIG. 9, /IO corresponds to a waveform when the Tr gate width of the CMOS flip-flop is reduced while /IOa corresponds to a waveform when the Tr gate width of the CMOS flip-flop is not so small. Here, the symbol “/” shows one signal line of a pair of complementary signal lines.
The IO lines IO and /IO may be pre-charged to a voltage not less than an operating voltage of a memory cell array in many cases. The CMOS flip-flop draws either of IO or /IO of the IO lines to a low level. The drawing speed is dependent on the capability of electric current, that is, the gate width of the transistor of Nch Tr included in the CMOS flip-flop. For this reason, although the drawing can be performed by about /IOa in the conventional sense amplifier in which the gate width of Tr is not so small, the differential electric potential of the IO lines is reduced in the sense amplifier on which the preamplifier is mounted because the drawing can be performed by only about /IO. As a result, this results in degradation of amplification speed and the speed degradation of the whole read pass of a data amplifier that amplifies the differential electric potential of the IO lines in a peripheral circuit region.
A second problem when the Tr gate width is reduced is that a data holding operation after a write operation (a rewriting operation) is delayed. In the write operation, the IO lines IO and /IO reverse electric potential of the bit lines BL and /BL via a transistor driven by the column switch line YS as shown in FIG. 10 when data to be written and data held in the sense amplifier are different from each other. In addition, FIG. 10 is a signal waveform chart showing a change of each signal line in the same configuration as that of FIG. 9. However, in connection with the bit lines BL and /BL shown in FIG. 10, the waveform when the Tr gate width of the CMOS flip-flop is reduced is shown as BL and /BL and the waveform when the Tr gate width of the CMOS flip-flop is not so small is shown as BLa and /BLa.
In the state where the column switch line YS is turning on transistors that connect the IO lines IO and /IO and the bit lines BL and /BL (in the state of YS=high), the IO line IO being driven draws electric charge of the bit line BL to reverse BL to a low level. If an ON time interval of the column switch line YS is terminated (the column switch line YS is usually a one-shot operation), the drive of the bit line BL after that is performed by the CMOS flip-flop. Although the bit line /BL is driven by the IO line /IO to a high level, the sense amplifier (waveform /BL) with the small Tr gate width has a further increased time arriving at an array voltage than that of the conventional sense amplifier (waveform /BLa) in which the Tr gate width is not so small.
Furthermore, since the bit lines BL and /BL are finely arranged, the resistance thereof is high. Far end portions of the bit lines BL and /BL require time for which the electric charge is completely pulled out. If the Tr gate width of the CMOS flip-flop is small, the bit line BL floats at a falling edge of the column switch line YS (waveform BL). Due to the reduction of the voltage Vgs between the gate and the source, the capability of electric current of Pch Tr further decreases and a time arriving at an array voltage level largely increases (waveform /BL).